The present invention generally relates to semiconductor manufacturing and, more particularly, to a method of protecting alignment marks from damage in a planarization process and a semiconductor device formed by the method.
One of the important aspects of fabricating integrated circuits (ICs) is to align layers in respect of one another in manufacturing of semiconductor components. That is, each layer may be precisely aligned so that the circuits formed therein match the design and thus work properly. However, as the dimension of the semiconductor device shrinks, the accuracy of aligning each layer becomes critical.
A tool known as a stepper is typically collaborated to align one layer with respect to another. A circuit pattern is projected optically from a photomask or reticle mounted in the stepper onto a layer formed on the semiconductor wafer with the help of the stepper. It is generally necessary to position or align the wafer being patterned in relation to the photomask. By using alignment marks defined on the wafer in previous processes, the alignment can be accomplished and the subsequent steps such as projecting the pattern onto the semiconductor wafer may proceed.
FIG. 1 is a schematic plan view which illustrates alignment mark areas 11 in a substrate 10. The substrate 10 may be overlaid by active areas 13, alignment mark areas 11 and a plurality of alignment mark trenches 12. The alignment mark trenches 12 may be arranged in an optional cross pattern and formed in the alignment mark areas 11. Furthermore, an alignment mark flattop 14 may be defined between adjacent alignment mark trenches 12.
When more layers are formed on the wafer, to planarize the wafer topography at intermediate processes, a global planarization technique, such as chemical and mechanical polish (CMP) may be used, which involves chemical etching and/or mechanical grinding/polishing a surface. The CMP or other planarization process, however, may damage the alignment marks on a wafer, resulting in a loading effect, as will be discussed in FIGS. 2a to 2f below.
Referring to FIG. 2a, a substrate 200, which may be p-type or n-type, may be provided. The substrate 200 may be further divided to an active area 210 on which electronic device features are formed and predefined alignment mark areas 211 with alignment mark trenches 207, which may be formed by plasma etching with a desired depth that may be determined by a function of the alignment radiation wavelength, e.g., 214.
A thin oxide layer 201 may then be grown on the substrate 200. Next, a silicon nitride (Si3N4) layer 202 may be formed on the oxide layer 201.
Referring to FIG. 2b, by photolithographic patterning and etching, a patterned silicon nitride layer 208 may be formed at the active area 210 so as to define shallow trench isolation (STI) regions 220.
Referring to FIG. 2c, an oxide layer 230 may be deposited on the silicon nitride layers 202 and 208, filling the STI regions 220, resulting in STI features 221.
Referring to FIG. 2d, the oxide layer 230 except those 231 on the alignment mark trenches 207 may be removed by an etching process followed by a planarization process. The planarization may include a residue removal process such as a CMP process, which may be accomplished by polishing the surface of a wafer by a polishing pad wetted with slurry mixed by basic solvent, abrasive and suspension fluid. The CMP process may be conducted until reaching a stop layer, for example, silicon nitride layer 202.
Referring to FIG. 2e, the residual oxide 231 and the silicon nitride layer 202 may then be removed. Next, a polysilicon layer 240 may be deposited.
Referring to FIG. 2f, when another planarization process such as CMP is conducted using the STI oxide 221 as the stop layer, the loading effect that may damage the alignment marks may occur because oxide 221 is considerably more rigid than polysilicon 240.